1. Field of the Invention
The present invention relates to a method for forming a semiconductor device isolation region to electrically isolate devices constituting a semiconductor integrated circuit on a silicon substrate.
2. Description of the Prior Art
There has been an increase in the capacity of VLSI (Very Large Scale Integrated Circuits) such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory) by four times every three years. At present, the DRAM which is mainly manufactured has the capacities of 256 Kb and 1 Mb. It is contemplated that DRAM's having the capacities of 4 Mb and 16 Mb which will be the mainstream in the future. Probably, there will be developed the DRAM having the capacities of 64 Mb and 256 Mb.
The device constituting an integrated circuit is made fine, so that integration can be improved in a limited chip area as described above. By way of example, the minimum dimension of a MOS transistor used in the 1 Mb DRAM is about 1 .mu.m. In the future, the above-mentioned minimum dimension will surely be reduced to 0.5 .mu.m and further to 0.25 .mu.m. Similarly, it is required to reduce a device isolation region for higher integration. In addition, it is necessary to reduce an isolation width from 1 .mu.m to about 0.5 .mu.m.
In general, the device isolation region is formed by a selective oxidation process. FIG. 2 shows the prior art in which the device isolation region is formed by the selective oxidation process. There will be described the conventional selective oxidation process with reference to FIGS. 2(a)-(d).
(1) As shown in FIG. 2 (a), the surface of a silicon substrate 21 is thinly oxidized to form a silicon oxide film 22 having a thickness of 100 to 700 .ANG.. Then, a silicon nitride film 23 having a thickness of 1000 to 2000 .ANG. is deposited over the silicon oxide film 22 by LPCVD (Low-Pressure Chemical Vapor Deposition). Then, a resist pattern 24 is formed to define an active region and a device isolation region constituting a semiconductor device. A region K covered by the resist pattern 24 is the active region. An opening 25 of the resist pattern 24 is a device isolation region S.
(2) The silicon oxide film 22 and silicon nitride film 23 in the opening 25 of the resist pattern 24 are etched by using the resist pattern 24 as an etching mask. Then, the resist pattern 24 is removed [see FIG. 2 (b)].
(3) When silicon is oxidized by a thermal oxidation process, oxygen is supplied to the exposed surface of the silicon substrate 21 through the opening 25 so as to oxidize the surface of the silicon substrate 21. Consequently, a silicon oxide film 26 is formed. In the active region K, the surface of the silicon substrate 21 is covered by the silicon nitride film 23. Consequently, the oxygen is not supplied to the silicon substrate 21, so that the silicon oxide film is not grown. In the vicinity of the opening 25, the oxygen is diffused through the thin silicon oxide film 22. Consequently, the silicon substrate 21 is oxidized. In addition, the silicon oxide film 26 is widely grown so as to push up the silicon nitride film 23 in the direction of an arrow A. The silicon oxide film 26 is extended below the silicon nitride film 23 so as to form a region 27 having a length of d. The region 27 is generally called a bird's beak [see FIG. 2 (c)].
(4) The silicon nitride film 23 is removed by a heated phosphoric acid solution. Then, the silicon oxide film 22 is removed by a diluted hydrofluoric acid solution. Thus, there is completed device isolation steps by the selective oxidation process [see FIG. 2 (d)].
Then, the semiconductor device such as a transistor is formed in the region 27 in which the surface of the silicon substrate 21 is exposed. The semiconductor devices are electrically isolated from each other by the silicon oxide film 26.
As described above, the device isolation region can be formed very easily by the selective oxidation process. Therefore, the selective oxidation process has widely been used as the device isolation technique of the semiconductor device.
However, it is required to reduce the device isolation region for the high integration of the semiconductor integrated circuit. In addition, it is necessary to reduce an isolation width from 1 .mu.m to about 0.5 .mu.m. The selective oxidation process has the following problems with respect to the reduction of the device isolation region. Consequently, it is difficult to use the selective oxidation process as the device isolation technique of the semiconductor integrated circuit having the higher integration.
Referring to the selective oxidation process in FIG. 2 (c), the thick silicon oxide film 26 for electrically isolating the devices is grown in the opening 25 of the silicon nitride film 23 as the device isolation region S. In addition, the intrusion of the silicon oxide film 26, which is a bird's beak 27, is generated in the active region K covered by the silicon nitride film 23. The bird's beak 27 has a width of d. Consequently, the isolation region is enlarged by a width of 2d on its both sides. On the other hand, the active region K is reduced by 2d. By way of example, if the width d is 0.3 .mu.m and the minimum pattern opening width is 0.4 .mu.m in a photolithographic step, the device isolation region is enlarged by 0.6 .mu.m on its both sides. Consequently, the formable minimum isolation width is 1.0 .mu.m. At present, there is required the device isolation region having a width which is a little less than 0.5 .mu.m as described above. Consequently, it is more difficult to form the device isolation region by the selective oxidation process.
It is an object of the present invention to provide a method for forming a semiconductor device isolation region corresponding to its fineness which is required with the high integration of a semiconductor integrated circuit.